The present invention relates to a method of producing a semiconductor device.
A bipolar transistor suitable for use within the high frequency range or suitable as a high speed switching element is required to have a great gain band product. In order to increase the gain band product of the bipolar transistor, it is necessary to make the element size smaller and especially to reduce the base transit time of the minority carriers. Most of the silicon transistors which are currently used are of the planar type, and their emitters and bases are formed by impurity diffusion. In such a case, when the dimension of the emitter is small, the junction plane of the emitter and the base becomes curved, and the effective base transit time depends not only on the base width but also on the collector-base junction depth. Accordingly, for improving the gain band product of the bipolar transistor, it is necessary to reduce the base width as well as the collector-base junction depth. Thus, the problem is to how to realize a shallow diffusion junction.
A conventional bipolar npn transistor is of the structure shown in FIG. 1. On a p.sup.- -type silicon substrate 1 are formed an n.sup.+ -type buried layer 2 and an n-type epitaxial layer 3. A p.sup.+ -type isolation region 4 for element isolation is formed in the epitaxial layer 3. A p-type base region 5 is formed at the part of the island epitaxial layer 3 isolated by the isolation region 4, and an n.sup.+ -type emitter region 6 is formed in the base region 5. A diffusion layer 7 reaching to the n.sup.+ -type buried layer 2 for connection with the collector is formed in another part of the epitaxial layer 3. An oxide film 8 is formed on the n-type epitaxial layer 3 by thermal oxidation. Aluminum electrodes 10, 11 and 12 for connection with the emitter region 6, the base region 5, and the diffusion layer 7 for connection with the collector are formed thereover through contact holes 9a, 9b and 9c, respectively.
In a bipolar transistor of such a structure, when the depth of the base region 5 is made small, the base resistance increases accordingly. Especially when the base region 5 becomes extremely shallow, the base resistance depends on the distance l between the emitter side end of the base contact hole 9b and the emitter region 6. This distance l is determined by the relative positions of the diffusion windows for the emitter region 6 and the base contact holes. This relation is in turn determined by the photoetching technique. With the current photoetching technique, it is difficult to make the distance l less than 1.5 .mu.m. This places a limit on the reduction of the base resistance.
Taking an I.sup.2 L (Integrated Injection Logic) element which is a bipolar logic element as an example, a conventional I.sub.2 L is of the structure shown in FIG. 2. In the p.sup.- -type silicon substrate 1 are formed the n.sup.+ -type buried layer 2 and the n-type epitaxial layer 3. The epitaxial layer 3 is isolated by the p.sup.+ -type isolation region 4. A p-type injector 13 and a p-type base region 14 are formed in the epitaxial layer 3. A plurality of n.sup.+ -type collector regions 15a, 15b are formed in the base region 14. The oxide film 8 is formed on the epitaxial layer 3 by thermal oxidation. On the oxide film 8 are formed through the contact holes 9 the collector regions 15a, 15b, the base region 14, rhw injector 13, and aluminum electrodes 16a, 16b, 17, 18 and 19 connected with an extension 2' of the n.sup.+ -type buried layer 2.
An I.sup.2 L of such a structure is a bipolar logic element of a composite structure incorporating a vertical npn transistor of the reverse operation type wherein the emitter and the collector of a normal transistor are reversed, and a lateral pnp transistor using the base of the vertical npn transistor as the collector. With such an I.sup.2 L, since the vertical npn transistor as the inverter is inverted, the emitter-base junction area is vastly greater than the collector-base junction area so that a sufficiently high speed operation of the bipolar element may not be attained. Thus, since carrier injection into the base region is performed from the entire emitter region surrounding the part immediately below the collector region, the effective base width becomes great, the current amplification factor becomes small, and the gain band product becomes small. As a result, the performance of the I.sup.2 L is degraded, and especially the switching speed is suppressed.
An I.sup.2 L which is free of such defects is described in IEDM Technical Digest (1979), pp. 201 to 204, "Sub-Nanosecond Self-Aligned I.sup.2 L/MTL Circuits". A polycrystalline silicon layer in which is doped an n.sup.+ -type impurity to a high concentration is used as the collector region in this I.sup.2 L. The base contact holes and the collector region are formed by the self-aligning technique utilizing the thickness difference with the silicon oxide film. The base region exposed at the surface of the substrate is covered with a metal to decrease the base resistance, allowing a structure such that the ratio of the emitter-base junction area to the collector-base junction area may approach 1. This I.sup.2 L shows the best performance of 0.8 nsec in minimum propagation delay time among the conventional I.sup.2 Ls. However, this I.sup.2 L also has many problems. The method for fabricating this element will be described in detail with reference to the attached drawings.
First, an n-type epitaxial layer 23 is formed in an n.sup.+ -type semiconductor substrate 22a. A high-concentration n.sup.+ -type semiconductor film 22b is formed at the surface of the substrate 22a to provide the emitter region (FIG. 3A).
Next, a silicon nitride layer 24 is deposited to a thickness of 1,000 A, as shown in FIG. 3B. After removing desired parts of the silicon nitride layer, the n-type epitaxial layer 23 thereunder is selectively etched. A heat treatment is performed to form a silicon oxide layer 25 of about 1.0 to 1.5 .mu.m thickness on the etched part. Since this silicon oxide layer 25 is formed to surround the periphery of the I.sup.2 L gate, it is also called the oxide film collar or the oxide isolation layer. This silicon oxide layer functions to isolate the gates of the I.sup.2 L from one another and to improve the injection efficiency of the minority carriers injected from the emitter to the base. After removing all of the silicon nitride layer 24, a silicon oxide layer is again formed to a thickness of 5,000 A. By opening a desired part of the silicon oxide layer, a silicon oxide layer 26 is formed (FIG. 3C).
After forming a base region 27 and an injector region 28, an arsenic-doped polycrystalline silicon film 29 is deposited to a thickness of 3,000 A, and a CVD silicon oxide layer (CVD-SiO.sub.2) 30 is deposited thereover to a thickness of 3,000 A. The CVD-SiO.sub.2 is patterned by the photoetching technique. Using the CVD-SiO.sub.2 pattern 30 as a mask, the arsenic-doped polycrystalline silicon film is etched with a solution of a mixture of HF:HNO.sub.3 :CH.sub.3 COOH=1:3:8 (FIG. 3D). The selectively left portion of the arsenic-doped polycrystalline silicon film 29 exists on the base region 27 for forming the collector region of the I.sup.2 L, and is used for connection with the collector electrode.
After forming a collector region 31 by diffusion using the arsenic-doped polycrystalline silicon film 29 as a diffusion source, the structure is thermally oxidized at a low temperature (700.degree. to 900.degree. C.). At this time, a silicon oxide film 32b of about several hundred A thickness is formed on the base region 27 and the injector region 28, and a silicon oxide film 32a of about 1,000 to 2,000 A thickness is formed on the side surface of the arsenic-doped polycrystalline silicon film 29. This is because the growing speed of the high-concentration n.sup.+ -type semiconductor layer is greater by a factor of several to several tens that of the low-concentration n.sup.+ -type semiconductor layer when oxidized at a low temperature (700.degree. to 900.degree. C.). Next, for reducing the contact resistance with metal electrode layer, ion implantation of high-concentration p.sup.+ -type ions is performed to form the injector region 28 and an outer base region 27' by diffusion (FIG. 3E).
Then, the silicon oxide film 32b on the injector region 28 and the outer base region 27' is etched by the self-aligning technique. All the contact holes are opened by the photoetching technique. After coating a metal electrode layer, electrode isolation is performed to form a base-connecting electrode 33, an injector-connecting electrode 34, and an emitter-grounding electrode 35 to provide an I.sup.2 L (FIG. 3F). FIG. 4 shows a plan view of FIG. 3F, and FIG. 5 shows a sectional view along the line V--V of FIG. 4.
With an I.sup.2 L fabricated by the above process, the electrodes of the base, the injector, and the emitter may be formed from the metal electrode layer, and the collector electrode may be formed from the arsenic-doped polycrystalline silicon layer, providing the various advantages described above. However, this method of fabricating an I.sup.2 L has various problems to be described below.
In the process shown in FIG. 3D, when etching the arsenic-doped polycrystalline silicon film using the CVD-SiO.sub.2 film pattern 30 as a mask, isotropic etching using a mixture of HF, HNO.sub.3, and CH.sub.3 COOH as a liquid etchant is used. Accordingly, the polycrystalline film is side etched to a depth corresponding to its film thickness, so that the CVD-SiO.sub.2 film 30 overhangs. When the arsenic-doped polycrystalline silicon film 29 is oxidized under such conditions, the silicon oxide film 32a grows in an anomalous form at the circumferential surface of the arsenic-doped polycrystalline silicon film 29, moving the underlying CVD-SiO.sub.2 pattern 30 upward. This disadvantageously tends to cause a disconnection of the base-connecting electrode crossing the arsenic-doped polycrystalline silicon film 29. Furthermore, since this arsenic-doped polycrystalline silicon film 29 is used as an interconnection layer for connections between the elements, this also tends to cause a disconnection from the second interconnection layer crossing thereover at the parts of the oxide film other than the element regions.
Secondly, it is impossible to make the arsenic-doped polycrystalline silicon film thicker than 3,000 A for preventing this overhanging. It follows from this that it is impossible to reduce the resistance of the arsenic-doped polycrystalline silicon film as the wiring for connection with the collector electrode. Furthermore, since the arsenic-doped polycrystalline silicon film 29 is thermally oxidized at a low temperature (700.degree. to 900.degree. C.) in the process shown in FIG. 3E, the wiring width becomes smaller and the wiring resistance becomes greater accordingly.
Thirdly, as shown in FIG. 3E, as a method for forming the base contact holes and the collector region by the self-aligning technique, different growing speeds of the silicon oxide film by low temperature oxidation of semiconductor layers due to different kinds of impurities or different impurity concentrations are utilized. The silicon oxide film 32a obtained by low temperature oxidation of the n.sup.+ -type semiconductor layer of high concentration is formed to be several times thicker than the silicon oxide film 32b formed on the p.sup.- -type semiconductor layer of low impurity concentration as the temperature for oxidation becomes lower. However, such a thick silicon oxide film is inferior in denseness, resulting in inferior insulating characteristics. Especially, when the silicon oxide film obtained by oxidizing at 800.degree. C. the n.sup.+ -type polycrystalline silicon layer of high impurity concentration is etched in an HF-type solution, the insulating characteristics are very inferior. Although a silicon oxide film of 1,000 A thickness formed by oxidation of a single-crystalline silicon layer at a high temperature (above 1,000.degree. C.) has a breakdown voltage of 80 to 90 V, the silicon oxide film of 2,000 A thickness described above has a breakdown voltage of 10 to 20 V or less, occasionally becoming zero. When observations are made after thermal oxidation, the silicon oxide film 32a, grown on both sides of the arsenic-doped polycrystaline silicon film 29 over the base region 27 formed in the single-crystalline silicon layer, grows less at the contact part with the single-crystalline silicon layer (base region 27) and is recessed as in FIG. 6A. Due to this, when the silicon oxide film 32b at both sides of the arsenic-doped polycrystalline silicon film is etched by an HF-type etchant, the silicon oxide film 32a of the arsenic-doped polycrystalline silicon film 29 is inferior in denseness and weakly resistant to the etchant. Furthermore, since the contact part with the base region 27 is thinner as compared with other parts, the lower side surface of the arsenic-doped polycrystalline silicon film 29 of the collector region 31 is etched as shown in FIG. 6B, exposing the n.sup.+ -type collector region 31 formed by using the polycrystalline silicon film 29 as a diffusion source from the side surface of the polycrystalline silicon film 29. As a result, when the base connecting electrode 33 is formed, the electrode 33 contacts the exposed part of the collector region 31, thereby short-circuiting the base and the collector.